This is not something that is specified in the PSoC 3 datasheet. Almost all designs will have the LCD in close proximity to the chip. The transitions are slow enough, and the load of the LCD would prevent reflections so that is not the issue, the issue would be more of the resistance of the path to the LCD as well as any noise interference. Noise we cant do anything about in the chip. Resistance will cause a drop in the voltage, so yes, that would affect the bias levels. The way to correct for this would be to adjust the bias higher.
