Designing with the Xilinx Virtex®-6 PCIe Gen2 Endpoint Block

[Bobgf]

Hello,

To achieve PCIe x8, what is the optimum solution? Spartan6 or Virtex6? Using FPGA onchip transceiver or exteranl controller for x8? Which package of FPGA is preffered? Is the IP core available? Is there a dev. kit available?

Thanks,

Bob

[npoureh]

Bob,

Currently, there are no PCIe x8 soft IP cores available for the Spartan-6 family (x1 hard IP and x4 soft IP only), so your best option would be to use the Virtex-6 family with the integrated PCIe x8 hard IP core (the V6 GTX transceivers will be used to implement the PCIe PHY). The Xilinx ML605 board supports PCIe x8 using the V6LX240T device.

In regards to which V6 package to use, it really depends on your application and the required number of I/Os.

Regards,

Nasser Poureh

[Bobgf]

Nasser,

Thanks for your replay.

Assume using V6LX240T, there are two PCIe blocks inside. Does it mean two SSD devices can be attached this FPGA? To connect two SSD devices, is it possible to configure both blocks as root port?

Regards,

Bob

[npoureh]

Bob,

Each PCIe block in V6 can be configured as an Endpoint or Root Port.

Regards,