- Subscribe to RSS Feed
- Mark Topic as New
- Mark Topic as Read
- Float this Topic to the Top
- Bookmark
- Subscribe
- Printer Friendly Page
S6 DDR3 EDK Simulation Problem
- Mark as New
- Bookmark
- Subscribe
- Subscribe to RSS Feed
- Highlight
- Email to a Friend
- Report Inappropriate Content
07-05-2010 10:36 AM
Hi all,
I build a simple edk project for the S6 LX150T Dev board with just an mpmc and a uart.
I am trying to simulate the project with modelsim but i have problems with mcb and the ddr3.
I connected the micron ddr3 model with the tb as:
rzq_pulldown3 : PULLDOWN port map(O => fpga_0_MCB_DDR3_rzq_pin);
zio_pulldown3 : PULLDOWN port map(O => fpga_0_MCB_DDR3_zio_pin);
cke_pulldown3 : PULLDOWN port map(O => fpga_0_MCB_DDR3_mcbx_dram_cke_pin);
odt_pulldown3 : PULLDOWN port map(O => fpga_0_MCB_DDR3_mcbx_dram_odt_pin);
rst_pulldown3 : PULLDOWN port map(O => fpga_0_MCB_DDR3_mcbx_dram_ddr3_rst_pin);
mcb3_dram_dqs_vector <= (fpga_0_MCB_DDR3_mcbx_dram_udqs_pin & fpga_0_MCB_DDR3_mcbx_dram_dqs_pin);
mcb3_dram_dqs_n_vector <= (fpga_0_MCB_DDR3_mcbx_dram_udqs_n_pin & fpga_0_MCB_DDR3_mcbx_dram_dqs_n_pin);
mcb3_dram_dm_vector <= (fpga_0_MCB_DDR3_mcbx_dram_udm_pin & fpga_0_MCB_DDR3_mcbx_dram_ldm_pin);
u_mem_c3 : ddr3 generic map (
DEBUG => 1
)
port map(
ck => fpga_0_MCB_DDR3_mcbx_dram_clk_pin,
ck_n => fpga_0_MCB_DDR3_mcbx_dram_clk_n_pin,
cke => fpga_0_MCB_DDR3_mcbx_dram_cke_pin,
cs_n => '0',
ras_n => fpga_0_MCB_DDR3_mcbx_dram_ras_n_pin,
cas_n => fpga_0_MCB_DDR3_mcbx_dram_cas_n_pin,
we_n => fpga_0_MCB_DDR3_mcbx_dram_we_n_pin,
dm_tdqs => mcb3_dram_dm_vector,
ba => fpga_0_MCB_DDR3_mcbx_dram_ba_pin,
addr => fpga_0_MCB_DDR3_mcbx_dram_addr_pin,
dq => fpga_0_MCB_DDR3_mcbx_dram_dq_pin,
dqs => mcb3_dram_dqs_vector,
dqs_n => mcb3_dram_dqs_n_vector,
tdqs_n => open,
odt => fpga_0_MCB_DDR3_mcbx_dram_odt_pin,
rst_n => fpga_0_MCB_DDR3_mcbx_dram_ddr3_rst_pin
);and compiling the memory model with:
Vlog +incdir+. +define+x1Gb +define+MAX_MEM +define+sg187E +define+x16 ddr3.V
I am not very familiar with the DDR3 interface so I cannot conclude whats going wrong but the system hangs without managing to access the memory. I am getting the following while the mcb constantly tries to precharge the same bank row col again and again
#
system_tb.u_mem_c3.cmd_task: at time 16896251.0 ps INFO: Precharge bank 7
# system_tb.u_mem_c3.cmd_task: at time 16896251.0 ps INFO: Precharge bank 7# system_tb.u_mem_c3.data_task: at time 16897502.0 ps INFO: READ @ DQS= bank = 7 row = 1fff col = 000003fc data = ffff
after a while it stops responding with:
# system_tb.u_mem_c3.cmd_task: at time 16918752.0 ps INFO: Refresh
# system_tb.u_mem_c3.cmd_task: at time 17028752.0 ps INFO: Activate bank 7 row 1fff
# system_tb.u_mem_c3.cmd_task: at time 87233753.0 ps ERROR: tRFC maximum violation during No Op
Re: S6 DDR3 EDK Simulation Problem
- Mark as New
- Bookmark
- Subscribe
- Subscribe to RSS Feed
- Highlight
- Email to a Friend
- Report Inappropriate Content
07-08-2010 09:03 AM
Please open a WebCase with Xilinx support regarding this issue.
http://www.xilinx.com/support/clearexpress/websupp
Regards,
Bryan



