Spartan-6 LX150T Development Kit

[jlanglet]

Hi, I have tried to create an AXI based MB system with ISE 13.3, using the EDK/BSB and selecting the AXI Ethernet instead of Ethernet Lite.

The board files were downloaded from Avnet. The resulting mcb_ddr3_wrapper.ncf contains pins locations that are not correct and in conflict with the corresponding pins in system.ncf.

The system.ncf pins are correct and the same as those in the system.ucf file in the XPS project.

When building the system.xmp from ISE, I do get a lot of map error (of course).

When I do the same thing for a SP605 board, I get a working system "out of the box" (tested on a SP605 with lwip + webserver).

Have anyone else encountered similar problem with AXI based systems/BSB/Avnet 13.2 board files and the LX150T board?? 

Any idea how I get around these problems??

Best Regards,

Joakim Langlet

[npoureh]

I don't get the errors you are getting as the pin locations in UCF always override the pins in the wrapper files. The reason you see a discrepency between the wrapper file pins and system.ucf pins is becuase the tool thinks you are using MCB3 while in reality the board uses MCB4 (the default is MCB3 in the memory controller MPD file). In any case, add the following line to the DDR3 instantiation in your system.MHS file and rebuild your design:

PARAMETER C_MCB_LOC = MEMC4

Also, make sure the device is set to S6LX150T-3FGG676.

[jlanglet]

Thanks, I will give that a try. The errors only appear when I initiate the design from ISE. In that case there is no UCF file in play and the .ncf file rules. When building inside XPS, the .ucf file overrules the .ncf files of the wrappers with only warnings as the result. Initiating the design from ISE does seem to have one advantage. It seems to be easier to set parameters to XST. My design is time critical and partly asynchronous in my own IP blocks. I really need to control XST behavior by options. Maybe there is some better way to execise that XST control, but I am only a beginner in this business.

Should'nt the BSB set this parameter (PARAMETER C_MCB_LOC = MEMC4) when targeting this board?  It would certainly be good for newbies like me!

I am using the BSB and pointing to the Spartan-6 LX150T board.

I tought that this would point to the device S6LX150T-3FGG676.

The XPS project "Device" seems correect. How should I be more clear about this??

When I look in the MPD file of the DDR3 parts there is no parameter for device. Is there some other place where DEVICE is set?? 

Thanks for the hint! I will be very happy for any additional hints, since my experience in this field is somewhat lacking.

I will report the result on this thread tomorrow!

[npoureh]

1) There are no problems with using the ISE flow to have more control over the synthesis, most customers use this flow.

2) Since the memory controller pins are fixed in S6 devices, you either specify the C_MCB_LOC parameter in the MHS file or you specify the memory interface pins in UCF. You shouldn't need to do both. This is certainly a tool issue.

3) The reason I asked about the device, I wanted to make sure you have a version of the ISE that does support the S6LX150T device (an evaluation version of the ISE does not).

4) The memory device part number is a parameter in the axi_s6_ddrx IP (C_MEM_PARTNO) and that's the only place you set it.

[jlanglet · Accepted solution]

Thanks for the excellent advice. The system builds nicely now.

When using the ISE flow, I don't need to set the pins in the UCF file.

I guess that you refer to the XPS flow where both .ncf and .ucf contains the ddr3 LOC's, that must be a tool issue... I agree!!

Also, I still think that the BSB should be able to set the C_MCB_LOC parameter based on the board files.

After all, the purpose of the board file is to describe the board and its component and pins connected on the FPGA.

These are of course not an Avnet issues, but rather Xilinx issues.

Again, thank you, Your advice is much appreciated.