Good day,
I'm trying to follow the iSim DDR hw co-simulation UG818 tutorial with the LX9 microboard:
http://www.xilinx.com/support/documentation/sw_manuals/xilinx13_2/ug818_ddr2_mem_tutorial.pdf
https://secure.xilinx.com/webreg/clickthrough.do?cid=170335&license=RefDesLicense&filename=rdf0126_d...
Has anyone already tried it, or is there some specific reason that make it not possible?
My current status is:
- I could find all the parameters for the MIG IP core for the mddr from the EDK projects.
I've also checked that the core clock multiplier/divider are 4/1 in synch with the 100Mhz clock available in the LX9
- In step 3 (p15), for the custom UCF file I'm planning to use the UCF provided by Avnet and rename the nets to match the verilog
Ex : LPDDR_A0 -> mcb3_dram_a[0]
The only thing is that the core seems to use a differential clock (c3_sys_clk_n/c3_sys_clk_p) while we only have single ended in the LX9 (like: CLOCK_Y3)
How should I do in this case?
- When I'm following the document in the next part (4, p19), Ise seem to have HW co-simulation option only for the SP601/SP605 kits.
How to add the LX9 compatibility?
Thanks for your help,
Cheers
