Spartan-6 / OMAP-L138 Co-Processing Kit

[Georgios]

Hello,

I have been trying to run the Inter-Communication reference design and I am encountering a problem when running the SPI demo. While the FPGA should send back 0x55, it sends 0x00 instead. I don't know if these are related but I have programmed the FPGA using iMPACT and downloading the .bit file to the FPGA rather than using the .bat file, as everytime I was trying to use the .bat file for some reason the FPGA was not getting programmed.

This is the output in the Console window. All other demos (I2C, EMIF, UPP) run without problems

=================================================
=== SPI Communication Demo : Start
=================================================
SPI1_SCS0 test
    SPI1 SCS0 - CMD_RDID = 0xFF 0x20 0x20 0x17
    SUCCESS : Numonyx M25P64 SPI Flash Detected !
SPI1_SCS2 test
    SPI1 SCS2 - CMD_RDID = 0x00 0x00 0x00 0x00
    ERROR : Unexpected Response!
SPI1_SCS3 test
   Enabling SPI1_SCS3 => FPGA SPI Flash hardware switch ...
    SPI1 SCS3 - CMD_RDID = 0x00 0x01 0x02 0x15
    SUCCESS : Spansion S25FL032P Detected!
   Disabling SPI1_SCS3 => FPGA SPI Flash hardware switch ...
=================================================
=== SPI Communication Demo : FAILED ! (1 errrors)
=================================================

Any ideas what might be wrong?

Many Thanks,

Georgios

[AlbertaBeef]

Georgios,

I could explain this symptom if the FPGA was not running the correct design.

However, you seem to have proved that the FPGA is running the correct design

by confirming that the UPP and EMIF tests are passing.

Can you confirm that you get the following output for the 'f' command ?

> f

FPGA Status

FPGA ID = 0x1C

Version = 1.05

>

Regards,

Mario.

[Georgios]

Hi Mario,

Yes, I can confirm that this is the output from the FPGA after using the 'f'.

Georgios

[AlbertaBeef]

Georgios,

I have been reflecting on your issue, and cannot figure out what could be causing this.

Here is what I would do : observe the SPI interface signals with ChipScope.

In the tutorial, have you gone through the exercise of adding ChipScope to the I2C interface ?

If yes, can you do the same exercise for the SPI interface ?

If you already have the I2C debug ChipScope project, you can add a second ILA for the SPI interface.

This will give us insight into what is happenning.

Regards,

Mario.

[Georgios]

Thanks Mario,

I have already thought about using Chipscope to debug the SPI signals but at the moment I am having problems with the license voucher I received with the Eval Kit and I am not able to use ChipScope. Hopefully Avnet will rectify this problem soon so I can continue debugging the design using ChipScope.

Georgios

[Kingfisher]

Hi,

  I have just received the Co-processing eval board and getting the same symptoms as described above. Before I start delving into Chipscope, I would like to know if the problem was resolved?

Kingfisher.

[professor]

Hi Georgios and Kingfisher,

I was looking at this on my board and I came across something that might help.

Like you both, I too was seeing errors when running the SPI portion of the Inter-Communications Reference Design.

> f
FPGA Status
    FPGA ID = 0x0B
    Version = 1.05
> s

=================================================
=== SPI Communication Demo : Start
=================================================
SPI1_SCS0 test
    SPI1 SCS0 - CMD_RDID = 0xFF 0x20 0x20 0x17
    SUCCESS : Numonyx M25P64 SPI Flash Detected !
SPI1_SCS2 test
    SPI1 SCS2 - CMD_RDID = 0xFF 0xFF 0xFF 0xFF
    ERROR : Unexpected Response!
SPI1_SCS3 test
   Enabling SPI1_SCS3 => FPGA SPI Flash hardware switch ...
    SPI1 SCS3 - CMD_RDID = 0xFF 0x01 0x02 0x15
    SUCCESS : Spansion S25FL032P Detected!
   Disabling SPI1_SCS3 => FPGA SPI Flash hardware switch ...
=================================================
=== SPI Communication Demo : FAILED ! (1 errors)
=================================================

After looking through everything a bit more closely, I noticed that the reported FPGA ID (0x0B) did not match the one posted earlier by Mario (0x1C).  After going through everything again, I noticed that the FPGA was not reconfiguring when I run the ready_for_download/run_demo.bat script (and thus was still running the OOB factory test FPGA bitstream programmed into the SPI flash).  I added a pause statement to the end of the run_demo.bat script to keep the command prompt window from closing immediately and saw that the iMPACT program was not being properly located and thus explained why the FPGA was not being reconfigured.

I modified the run_demo.bat file to run the environment settings configuration script prior to calling for iMPACT, the script now contains the following:

echo Loading FPGA Design
call C:\Xilinx\13.1\ISE_DS\settings32.bat
impact -batch download.cmd
pause

After re-running the run_demo.bat file, I saw that the FPGA was indeed reconfiguring with the appropriate bitstream file.  So I re-ran the DSP application and saw much better results this time.

> f
FPGA Status
    FPGA ID = 0x1C
    Version = 1.05
> s

=================================================
=== SPI Communication Demo : Start
=================================================
SPI1_SCS0 test
    SPI1 SCS0 - CMD_RDID = 0xFF 0x20 0x20 0x17
    SUCCESS : Numonyx M25P64 SPI Flash Detected !
SPI1_SCS2 test
    SPI1 SCS2 - CMD_RDID = 0x55 0x55 0x55 0x55
    SUCCESS : FPGA Test Logic Detected!
SPI1_SCS3 test
   Enabling SPI1_SCS3 => FPGA SPI Flash hardware switch ...
    SPI1 SCS3 - CMD_RDID = 0xFF 0x01 0x02 0x15
    SUCCESS : Spansion S25FL032P Detected!
   Disabling SPI1_SCS3 => FPGA SPI Flash hardware switch ...
=================================================
=== SPI Communication Demo : PASSED !
=================================================

Oddly enough, notice the FPGA version reported is still 1.05 but the FPGA ID is now 0x1C which matches the example that was posted by Mario.

Can either of you take a look at this on your end, see if something similar is happening, and report back your findings?

Regards,

-Kevin

[Kingfisher]

Hi Kevin,

  From power on, I started CCS and ran the intercoms code without downloading anything to the FPGA. On entering “f” I get

FPGA Status

      FPGA ID = 0x0B

      Version = 1.05

On entering “s” I get

=================================================

=== SPI Communication Demo : Start

=================================================

SPI1_SCS0 test

      SPI1 SCS0 - CMD_RDID = 0xFF 0x20 0x20 0x17

      SUCCESS : Numonyx M25P64 SPI Flash Detected !

SPI1_SCS2 test

      SPI1 SCS2 - CMD_RDID = 0xFF 0xFF 0xFF 0xFF

      ERROR : Unexpected Response!

SPI1_SCS3 test

   Enabling SPI1_SCS3 => FPGA SPI Flash hardware switch ...

      SPI1 SCS3 - CMD_RDID = 0xFF 0x01 0x02 0x15

      SUCCESS : Spansion S25FL032P Detected!

   Disabling SPI1_SCS3 => FPGA SPI Flash hardware switch ...

=================================================

=== SPI Communication Demo : FAILED ! (1 errrors)

=================================================

I then downloaded the FPGA code using your modified batch file and then re-enter “f”

FPGA Status

      FPGA ID = 0x1C

      Version = 1.05

And then reenter “s”

=================================================

=== SPI Communication Demo : Start

=================================================

SPI1_SCS0 test

      SPI1 SCS0 - CMD_RDID = 0xFF 0x20 0x20 0x17

      SUCCESS : Numonyx M25P64 SPI Flash Detected !

SPI1_SCS2 test

      SPI1 SCS2 - CMD_RDID = 0x00 0x00 0x00 0x00

      ERROR : Unexpected Response!

SPI1_SCS3 test

   Enabling SPI1_SCS3 => FPGA SPI Flash hardware switch ...

      SPI1 SCS3 - CMD_RDID = 0x00 0x01 0x02 0x15

      SUCCESS : Spansion S25FL032P Detected!

   Disabling SPI1_SCS3 => FPGA SPI Flash hardware switch ...

=================================================

=== SPI Communication Demo : FAILED ! (1 errrors)

=================================================

So this has not corrected the error.

I have begun to use chipscope to decipher what is going on and found that  spi1_scs1 stays low during the SPI transfer, hence keeping the somi line disabled. I have included the Chipscope trace as an attachment.

  I hope this helps us to find a solution.

Kingfisher.

[AlbertaBeef]

Kingfisher,

That is a VERY interesting ChipScope capture !

The transaction we are debugging can be seen on SP1_SCS2, with SP1_SCS2 being "active low".

We can observe the return values of 0x55 inside the FPGA.

This transaction would work, except for the fact that SP1_SCS1 is low,

and has priority on the FPGA design's multiplexer for the SPI1_SOMI output.

The SPI1_SCS1 is obviously still configured to be "active high" and is

- "inactive" from the OMAP's point-of-view

but

- "active" from the FPGA's point-of-view.

The DSP application relies on an undetermined previous state for the polarity of SPI1_SCS1, which is not a good idea.

Can you try a new version fo the s6_omap_intercomms_spi.c source file (attached) which explicitly configure SPI1_SCS1 to be active low ?

The expected output is:

=================================================

=== SPI Communication Demo : Start

=================================================

SPI1_SCS0 test

      SPI1 SCS0 - CMD_RDID = 0xFF 0x20 0x20 0x17

      SUCCESS : Numonyx M25P64 SPI Flash Detected !

SPI1_SCS1_config

SPI1_SCS2 test

      SPI1 SCS2 - CMD_RDID = 0x55 0x55 0x55 0x55

      SUCCESS : FPGA Test Logic Detected!

SPI1_SCS3 test

   Enabling SPI1_SCS3 => FPGA SPI Flash hardware switch ...

      SPI1 SCS3 - CMD_RDID = 0x00 0x01 0x02 0x15

      SUCCESS : Spansion S25FL032P Detected!

   Disabling SPI1_SCS3 => FPGA SPI Flash hardware switch ...

=================================================

=== SPI Communication Demo : PASSED !

=================================================

Regards,

Mario